Title :
Design and optimization of silicon JFET in 180nm RF/BiCMOS technology
Author :
Shi, Yun ; Rassel, Robert M. ; Phelps, Richard A. ; Rainey, BethAnn ; Dunn, Jim ; Harame, David
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
Abstract :
In this paper, we discuss a method to extrapolate intrinsic and extrinsic Ron components for a JFET. The results provide the guideline to lower Ron, hence to achieve competitive “Ron vs. pinch off (Voff)” benchmark. The optimization impacts on channel length scaling and process variation are discussed. Besides, an improved RESURF condition is achieved using one of the experimental conditions. The optimized JFET demonstrates the 50% lowered Ron, low Voff of -2.75V, and high BVdss of 11V.
Keywords :
BiCMOS integrated circuits; JFET circuits; circuit optimisation; elemental semiconductors; extrapolation; integrated circuit design; silicon; RESURF condition; RF/BiCMOS technology; Si; channel length scaling; extrapolation; optimization impacts; process variation; silicon JFET; size 180 nm; voltage -2.75 V; voltage 11 V; Doping; Electric breakdown; JFETs; Junctions; Logic gates; Optimization; Radio frequency; JFET; Ron; Voff; avalanche breakdown;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010 IEEE
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-8578-9
DOI :
10.1109/BIPOL.2010.5667942
