A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator

This paper presents a high resolution and wide range offset calibration technique for high resolution comparators. The proposed calibration technique significant reduces the calibration capacitance from conventional 2ⁿ binary-scaled capacitors array to a small voltage-controlled capacitor. Furthermore, it utilizes inherent system clock to perform calibration and does not require extra clock phase. After proposed calibration, simulation result shows an offset of conventional dynamic comparators being reduced from 35 mV to 350 ¿V (one sigma) operating at 1 GHz in 65 nm CMOS technology with only 20 ¿W power in calibration.