• DocumentCode
    1645107
  • Title

    Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic

  • Author

    Johansson, Kenny ; Gustafsson, Oscar ; Dempster, Andrew G. ; Wanhammar, Lars

  • Author_Institution
    Dept. of Electr. Eng., Linkoping Univ., Sweden
  • Volume
    1
  • fYear
    2004
  • Firstpage
    197
  • Abstract
    In this paper an algorithm for realization of multiplier blocks using bitand digit-serial arithmetic is presented. Previously presented algorithms were designed for bit-parallel arithmetic and for that reason assumed no cost for shifts. It is shown that the new algorithm reduces the total complexity significantly.
  • Keywords
    adders; digital arithmetic; digital filters; digital signal processing chips; flip-flops; multiplying circuits; addition reduction; bit-parallel arithmetic; bit-serial arithmetic; complexity reduction; digit-serial arithmetic; digital signal processing; multiplier blocks; shift reduction; Adders; Algorithm design and analysis; Arithmetic; Circuits; Costs; Digital filters; Digital signal processing; Finite impulse response filter; Flip-flops; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrotechnical Conference, 2004. MELECON 2004. Proceedings of the 12th IEEE Mediterranean
  • Print_ISBN
    0-7803-8271-4
  • Type

    conf

  • DOI
    10.1109/MELCON.2004.1346807
  • Filename
    1346807
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1645107