• DocumentCode
    1645124
  • Title

    Impact Of Boundary-Scan Design On Delay Test

  • Author

    Vida-Torku, E. Kofi

  • fYear
    1992
  • Firstpage
    96
  • Keywords
    Application specific integrated circuits; Circuit testing; Clocks; Costs; Delay; Integrated circuit testing; Logic testing; Pins; System testing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1992. Proceedings., International
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-0760-7
  • Type

    conf

  • DOI
    10.1109/TEST.1992.527809
  • Filename
    527809
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1645124