High Mobility III-V Mosfet Technology

In recent years, fundamental interface issues have been overcome and GaAs MOS technology has advanced to the level of device fabrication. This development has been enabled by a molecular beam epitaxy (MBE) deposited Ga₂O₃ template with the unique property of unpinning the Fermi level on GaAs, and a GdGaO dielectric layer which provides required band offsets while neither disrupting the template nor creating a secondary interface. MOSFET wafers with an InGaAs channel layer are grown by MBE on III-V substrates including the high-k dielectric GdGaO/Ga₂O₃ stack (k cong 20). Electron mobilities exceeding 12,000 and 6,000 cm²/ Vs for sheet carrier concentration n_s of about 2.5 times 10¹² cm^-2 have been measured on InP and GaAs based MOSFET structures, respectively. Our enhancement-mode MOSFETs employ a new, implant-free device concept, which allows one to take advantage of high mobility in MOSFET channel layers. N-channel enhancement-mode GaAs MOSFETs have been fabricated with important DC figures of merit such as maximum drain current and transconductance approaching predicted performance