Architecture optimization for H.264/AVC propagate partial SAD engine in HDTV application

This paper presents one compact propagate partial SAD (PPSAD) engine for H.264/AVC in HDTV application. Firstly, by using mode reduction technique, redundant registers in original PPSAD structure is removed. Secondly, circuit optimization is applied on the whole structure. Redundant adders within processing element (PE) and PE rows are removed. With TSMC 0.18 um technology under worst case conditions (1.62 V, 125°C), the proposed architecture can achieve 27.4% to 33.2% reduction of hardware and 11.7% saving in power consumption. When it is applied to parallel processing of HDTV 1080 p real-time encoder, about 10 k gates can be saved compared with previous design.