Title :
An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy
Author :
Lee, Joohwan ; Park, Kihyun ; Kang, Sungho
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
A novel built-in redundancy analysis (BIRA) is proposed for embedded memories. The proposed BIRA algorithm has two phases. In the first phase, detected faults are collected to area-efficient fault storing content addressable memory (CAM). In order to determine a correct repair solution, spare memories are allocated in the second phase using linear feedback shift register (LFSR) with fast analyzing speed. Experimental results show that the proposed BIRA algorithm achieves optimal repair rate and very low area overhead.
Keywords :
circuit feedback; content-addressable storage; embedded systems; redundancy; shift registers; 2D redundancy; BIRA algorithm; area-efficient built-in redundancy analysis; area-efficient fault storing content addressable memory; embedded memories; linear feedback shift register; optimal repair rate; phase allocation; Algorithm design and analysis; Built-in self-test; CADCAM; Computer aided manufacturing; Electrostatic precipitators; Hardware; Phase detection; Phased arrays; Redundancy; System-on-a-chip; built-in redundancy analysis; built-in self-test; embedded memory; optimal repair rate;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423846
