Title :
Direct tunneling current model for circuit simulation
Author :
Chang-Hoon Choi ; Kwang-Hoon Oh ; Jung-Suk Goo ; Zhiping Yu ; Dutton, R.W.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
This paper presents a compact direct tunneling current model for circuit simulation to predict ultra-thin gate oxide (<2.0 nm) CMOS circuit performance by introducing an explicit surface potential model with quantum-mechanical corrections. It demonstrates good agreement with the results from the numerical solver and measured data for the very-thin gate oxide thicknesses ranging 1.3-1.8 nm.
Keywords :
CMOS integrated circuits; circuit simulation; circuit stability; integrated circuit modelling; leakage currents; surface potential; tunnelling; 1.3 to 1.8 nm; CMOS circuit performance; circuit simulation; direct tunneling current model; explicit surface potential model; gate oxide thicknesses; numerical solver; quantum-mechanical corrections; ultra-thin gate oxide; Circuit optimization; Circuit simulation; Electrons; Leakage current; MOSFETs; Predictive models; Semiconductor device modeling; Thickness measurement; Tunneling; Voltage;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824256
