Design techniques to Minimize the yield loss for general purpose ASIC/SOC Devices

Since the manufacturing process has been scaled down under 65 nm process, semiconductor industries have suffered from the yield loss although the total number of manufactured die has continuously increased. In order to overcome this ironic situation, industries have focused on the improvement of process technology, but reducing pattern size without a break makes this process improvement difficult. In this paper, we present the circuit techniques based on body and gate-length biasing to resolve this yield loss problem. Our application results show that up to 28% parametric yield can be improved by applying the proposed circuit techniques. In addition, the application of proposed methods does not need to have the specific platform since our methodology is quite easy to plug in general purpose application.