Title :
Low temperature (Ba,Sr)TiO/sub 3/ capacitor process integration (LTB) technology for gigabit scaled DRAMs
Author :
Hieda, K. ; Eguchi, K. ; Nakahira, J. ; Kiyotoshi, M. ; Nakabayashi, M. ; Tomita, H. ; Izuha, M. ; Aoyama, T. ; Niwa, S. ; Tsunoda, K. ; Yamazaki, S. ; Lin, J. ; Shimada, A. ; Nakamura, K. ; Kubota, T. ; Asano, M. ; Hosaka, K. ; Fukuzumi, Y. ; Ishibashi,
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
Low temperature (600/spl deg/C) (Ba,Sr)TiO/sub 3/ (BST) capacitor process integration (LTB) based on a SrRuO/sub 3/ (SRO) electrode is proposed to achieve gigabit scaled and embedded DRAMs. The BST crystallization temperature is successfully reduced by SRO, which has the same perovskite structure as the BST film. Chemical Mechanical Polishing (CMP) and O/sub 3/ water etching are developed for storage node (SN) electrode and plate (PL) electrode patterning. A new low temperature post anneal method is also proposed in order to reduce oxygen vacancies at the top electrode-BST interface.
Keywords :
DRAM chips; annealing; barium compounds; chemical mechanical polishing; chemical vapour deposition; crystallisation; etching; ferroelectric capacitors; ferroelectric storage; ferroelectric thin films; strontium compounds; (Ba,Sr)TiO/sub 3/ capacitor; 0.1 mum; 0.13 mum; 600 C; BaSrTiO/sub 3/-SrRuO/sub 3/; O vacancy reduction; O/sub 3/; O/sub 3/ water etching; SrRuO/sub 3/ electrode; chemical mechanical polishing; crystallization temperature; embedded DRAMs; gigabit scaled DRAMs; low temperature post anneal method; low temperature process integration technology; perovskite structure; plate electrode patterning; storage node electrode patterning; Annealing; Binary search trees; Capacitors; Chemicals; Crystallization; Electrodes; Etching; Temperature; Tin; Water storage;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824268
