DocumentCode
1645829
Title
Decoder Design for Non-Binary LDPC Codes
Author
Liu, Fei ; Li, Haitao
Author_Institution
Coll. of Electron. Inf. & Control Eng., Beijing Univ. of Technol., Beijing, China
fYear
2011
Firstpage
1
Lastpage
4
Abstract
Abstract-Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. In this paper, we give the different initial step for different modulation and present a hardware implementation of the extended min-sum (EMS) decoding algorithm for non-binary LDPC codes. Moreover, an FPGA simulation over GF(16) is given to demonstrate the efficiency of the presented techniques.
Keywords
Galois fields; decoding; error correction codes; field programmable gate arrays; modulation; parity check codes; EMS decoding algorithm; FPGA simulation; GF(16); code length; decoder design; error correcting code; extended min-sum decoding algorithm; low-density parity check code; modulation; nonbinary LDPC codes; Algorithm design and analysis; Bit error rate; Computer architecture; Decoding; Hardware; Modulation; Parity check codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communications, Networking and Mobile Computing (WiCOM), 2011 7th International Conference on
Conference_Location
Wuhan
ISSN
2161-9646
Print_ISBN
978-1-4244-6250-6
Type
conf
DOI
10.1109/wicom.2011.6040195
Filename
6040195
Link To Document