• DocumentCode
    1645870
  • Title

    An 8.9mW 25Gb/s inductorless 1:4 DEMUX in 90nm CMOS

  • Author

    Sekiguchi, Takayuki ; Amakawa, Shuhei ; Ishihara, Noboru ; Masu, Kazuya

  • Author_Institution
    Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama, Japan
  • fYear
    2009
  • Firstpage
    404
  • Lastpage
    407
  • Abstract
    A low-power inductorless 1:4 DEMUX in 90 nm CMOS is presented. It is capable of operating at 25 Gb/s with a power supply voltage of 1.05 V, and the power consumption is 8.9 mW. Its area is 29 × 40 ¿m2. The DEMUX consists primarily of latches in differential pseudo-NMOS logic style. This logic style has a near-rail-to-rail logic swing and is much more scalable under low Vdd than the current-mode logic, commonly used for high-performance SerDes. It is also compatible with the conventional CMOS logic, and direct connection with CMOS logic gates is possible without logic level conversion. The low power, small footprint, and reasonable speed could be beneficial for chip-to-chip communication within a multi-chip module.
  • Keywords
    CMOS logic circuits; demultiplexing; flip-flops; CMOS logic gate; bit rate 25 Gbit/s; differential pseudoNMOS logic; inductorless demultiplexer; latches; near rail-to-rail logic; power 8.9 mW; size 29 mum; size 40 mum; size 90 nm; voltage 1.05 V; CMOS logic circuits; CMOS technology; Clocks; Frequency conversion; Integrated circuit interconnections; Latches; MOSFETs; Packaging; Paper technology; Voltage; CMOS; DEMUX; divider; multi-phase clock architecture; near-rail-to-rail logic swing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2009 International
  • Conference_Location
    Busan
  • Print_ISBN
    978-1-4244-5034-3
  • Electronic_ISBN
    978-1-4244-5035-0
  • Type

    conf

  • DOI
    10.1109/SOCDC.2009.5423868
  • Filename
    5423868