Title :
Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides
Author :
Kubicek, S. ; Henson, W.K. ; De Keersgieter, A. ; Badenes, G. ; Jansen, P. ; van Meer, H. ; Kerr, D. ; Naem, A. ; Deferm, L. ; De Meyer, K.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
Optimum device design for high performance applications has been investigated assuming a fixed oxide thickness of 2.5 nm and supply voltage of 1.5 V. The optimal performance is achieved by minimizing parasitic effects. The influence of experimental splits in source/drain (S/D) extension dose, S/D HDD dose and spike RTA on the reduction of series resistance and poly-depletion effect is studied. The role of the HALO implantation in optimization is investigated in detail.
Keywords :
CMOS integrated circuits; MOSFET; ion implantation; rapid thermal annealing; semiconductor device measurement; 1.5 V; 2.5 nm; 2.5 nm NO gate oxides; HALO implantation; S/D HDD dose; advanced CMOS devices; fixed oxide thickness; high performance applications; intrinsic transistor performance; optimum device design; parasitic effects; poly-depletion effect; series resistance; short channel effect; source/drain extension dose; spike RTA; supply voltage; CMOS process; Doping profiles; Electric resistance; Implants; Limiting; Parasitic capacitance; Thermal resistance; Threshold voltage; Transistors; Tunneling;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824276
