A CMOS 3.2 Gb/s 4-PAM serial link transceiver

Author

Jeong, Jikyung ; Lee, Jeongjun ; Burm, Jinwook

Author_Institution

Dept of Electron. Eng., Sogang Univ., Seoul, South Korea

fYear

2009

Firstpage

408

Lastpage

411

Abstract

A CMOS 3.2-Gb/s multilevel pulse amplitude modulation (PAM) transceiver is proposed. By using 4-PAM signaling, symbol rate is effectively decreased compared to the binary signaling. Data transmission is executed through current mode instead of voltage mode for high data transmission rate. 2⁵-1 pseudo random bit sequence (PRBS) generator was designed on-chip for built-in self test (BIST) operation. The CMOS transceiver is designed in 0.18 Â¿m CMOS process. It achieves 3.2-Gb/s data rate, and total power consumption is 148 mW.

Keywords

CMOS integrated circuits; built-in self test; data communication; power consumption; pulse amplitude modulation; random sequences; transceivers; 4-PAM serial link transceiver; 4-PAM signaling; BIST; CMOS; binary signaling; bit rate 3.2 Gbit/s; built-in self test; data transmission; multilevel pulse amplitude modulation transceiver; power 148 mW; pseudo random bit sequence generator; size 0.18 mum; Amplitude modulation; Automatic testing; Built-in self-test; CMOS process; CMOS technology; Data communication; Multiplexing; Pulse modulation; Transceivers; Transmitters; 4-PAM; CMOS; Serial link; multi level signaling; transceiver;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2009 International

Conference_Location

Busan

Print_ISBN

978-1-4244-5034-3

Electronic_ISBN

978-1-4244-5035-0

Type

conf

DOI

10.1109/SOCDC.2009.5423869

Filename

5423869