Title :
NMOS drive current reduction caused by transistor layout and trench isolation induced stress
Author :
Scott, G. ; Lutze, J. ; Rubin, M. ; Nouri, F. ; Manley, M.
Author_Institution :
Philips Semicond., San Jose, CA, USA
Abstract :
This paper describes a previously unreported phenomenon wherein NMOS transistors of identical gate length exhibit a significant sensitivity to layout. Drive current may be reduced up to 13%, depending on diffusion overlap of gate. Mobility reduction, induced by stress from the trench isolation edge, is the root cause of the performance degradation. PMOS devices are not affected. Simulation results show that stress varies strongly with distance from the trench edge, and with overall diffusion size. Stress is also a major component of narrow-width effects, and explains why Idsat scaling with W differs for NMOS and PMOS devices.
Keywords :
MOSFET; carrier mobility; diffusion; internal stresses; isolation technology; semiconductor device models; semiconductor device reliability; 0.2 mum; NMOS drive current reduction; NMOS transistors; SUPREM simulation; diffusion size; gate diffusion overlap; gate length; layout sensitivity; mobility reduction; narrow-width effects; performance degradation; simulation results; transistor layout; trench isolation induced stress; Degradation; Foundries; Isolation technology; MOS devices; MOSFETs; Photonic band gap; Stress; Testing;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824277
