Equivalent circuit model for thermal resistance of deep trench isolated bipolar transistors

An equivalent circuit model for thermal resistance of deep trench isolated bipolar transistors on conventional SOI and compound buried layer (CBL) substrates has been proposed to investigate the thermal resistance behaviour in a 3×3 array of similar devices. The model is based on 3D electro-thermal simulations with realistic boundary conditions for increased accuracy. The simulations and circuit model show an excellent agreement with the measurements. Results suggest that a separation in the range 2 to 4 μm between two adjacent devices in an array would be sufficient to limit the rise in thermal resistance due to thermal coupling.