Title :
Analysis and control of hysteresis in PD/SOI CMOS
Author :
Pelella, M.M. ; Fossum, J.G. ; Chiang, M.-H. ; Workman, G.O. ; Tretz, C.R.
Author_Institution :
Florida Univ., Gainesville, FL, USA
Abstract :
A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100 nm.
Keywords :
CMOS logic circuits; hysteresis; logic gates; silicon-on-insulator; 100 nm; hysteresis; partially depleted SOI CMOS inverter circuit; CMOS technology; Charge carrier processes; Delay effects; Hysteresis; Industrial control; MOSFET circuits; Physics; Propagation delay; Ultra large scale integration; Voltage;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824278
