Exploration and assessment of memory architectures for densely-deployed embedded sensor networks

Densely-deployed embedded sensor networks are susceptible to constraints associated with contention across a shared transport medium. To improve channel reliability, as well as average power consumption across the system, densely-deployed embedded sensor networks often leverage node-based neighbourhood data aggregation strategies. The tradeoff is that individual sensor nodes will have increased memory capacity and access requirements; where access requirements are determined by the memory transport bandwidth, the nature and frequency of the memory accesses, and the latencies associated with the memory storage mechanism. Individual sensor nodes consume power both directly based on the number/nature of memory operations, and indirectly through leakage current through latent circuitry. This paper considers the impact of different memory archetypes on performance of aggregation-related algorithms by individual nodes - specifically the scalability of number of required bus transactions and memory-related latencies with data-set size. The archetypes under consideration were: linear-addressing (RAM), content-based addressing (ternary CAM), and multi-dimensional addressing (Parks´). VHDL-specified MicroBlaze-based nodes, a 32 bit data-bus, and archetypical memories were implemented on a Virtex-5 development board. Operations central to aggregation algorithms (min, sum, count) were run using each type of memory on data-sets of 8 different sizes between 8 and 1024 data-points. Results suggest that appropriate selection of local-node memory architecture, can offer performance benefits in densely deployed sensor networks.