• DocumentCode
    1646079
  • Title

    High profile intra prediction architecture for H.264

  • Author

    He, Xun ; Zhou, Dajiang ; Zhou, Jinjia ; Goto, Satoshi

  • Author_Institution
    Grad. Sch. of IPS, Waseda Univ., Tokyo, Japan
  • fYear
    2009
  • Firstpage
    57
  • Lastpage
    60
  • Abstract
    This paper presents a new architecture for high performance intra prediction in H.264/AVC video coding standard, which can support H.264 high profile features. Our goal is to design an Intra prediction engine for Ultra High Definition (UHD) Decoder (4 K x 2 K @ 60 fps). The proposed architecture can achieve very stable throughput, which can process any H.264 intra prediction modes within 66 cycles. Comparing with previous design, this feature can guarantee the whole decoding pipeline to work efficiently. The proposed architecture can overlap data preparing time and prediction time, which can finish data loading and storing within 2 cycles pipeline stalls. We apply the combined module approach to achieve high throughput and low area cost for ultra high-definition video, which can support all H.264 features. The proposed architecture is verified to work at 81 MHz in a Xilinx V4 FPGA. It costs about 53.9 K Gates by using TSMC 90 nm and satisfies requirement of our UHD Decoder.
  • Keywords
    field programmable gate arrays; video codecs; video coding; H.264/AVC video coding standard; data loading; decoding pipeline; frequency 81 MHz; high profile intra prediction; size 90 nm; ultra high definition decoder; Automatic voltage control; Costs; Decoding; Engines; Hardware; High definition video; MPEG 4 Standard; Pipelines; Throughput; Video coding; H.264; High Profile; Intra Prediction; UHD;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2009 International
  • Conference_Location
    Busan
  • Print_ISBN
    978-1-4244-5034-3
  • Electronic_ISBN
    978-1-4244-5035-0
  • Type

    conf

  • DOI
    10.1109/SOCDC.2009.5423874
  • Filename
    5423874