RF potential of a 0.18-/spl mu/m CMOS logic technology

Author

Burghartz, J.N. ; Hargrove, M. ; Webster, C. ; Groves, R. ; Keenes, M. ; Jenkins, K. ; Edelstein, D. ; Logan, R. ; Nowak, E.

Author_Institution

DIMES, Delft Univ. of Technol., Netherlands

fYear

1999

Firstpage

853

Lastpage

856

Abstract

The RF potential of a 0.18-/spl mu/m CMOS logic technology is investigated, and suggestions for an optimization of the frequency responses (f/sub T/ and f/sub max/), the minimum noise figure (F/sub min/) and the 1/f-noise based on device layout, bias conditions, and type of gate dielectrics are made. N/sub 2/O gate oxide in place of nitrogen-implanted oxide is proposed to reduce the 1/f-noise, as well as the use of non-epi wafers and a thick top-metal layer for the implementation of high-Q inductors.

Keywords

1/f noise; CMOS logic circuits; Q-factor; UHF integrated circuits; frequency response; inductors; integrated circuit noise; integrated circuit technology; 0.18 micron; 1/f noise reduction; CMOS logic technology; N/sub 2/O; N/sub 2/O gate oxide; RF potential; bias conditions; device layout; frequency response optimisation; gate dielectrics; high-Q inductors; minimum noise figure; nonepi wafers; thick top-metal layer; CMOS logic circuits; CMOS technology; Cutoff frequency; Fingers; MOS devices; MOSFETs; Noise figure; Radio frequency; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.824283

Filename

824283