Title :
Impact of interconnect capacitance reduction on RF-Si device performance
Author :
Nakahara, Y. ; Yano, H. ; Hirayama, Takatsugu ; Suzuki, Y. ; Furukawa, A.
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Ibaraki, Japan
Abstract :
Ultra-low noise characteristics have been obtained in deep-sub-micron Si MOSFETs and Si MMICs by the new low-capacitance interconnect technique using polyimide inter-level dielectrics. The key issue is how to suppress the influence of interconnect parasitics due to the Si substrate. We have achieved 0.13 /spl mu/m Si nMOS with NF/sub min/ of 0.26 dB at 2 GHz and 6 GHz Si LNA with NF (50 /spl Omega/) of 2.2 dB and gain of 16.2 dB.
Keywords :
MMIC amplifiers; MOS integrated circuits; MOSFET; UHF integrated circuits; capacitance; dielectric thin films; elemental semiconductors; field effect MMIC; integrated circuit interconnections; integrated circuit noise; silicon; 0.13 micron; 0.26 dB; 16.2 dB; 2 GHz; 2.2 dB; 6 GHz; RF Si device performance; SHF; Si; Si LNA; Si MMICs; Si nMOSFET; Si substrate; UHF; deep-submicron Si MOSFETs; interconnect capacitance reduction; interconnect parasitics; low-noise amplifier; polyimide inter-level dielectrics; ultra-low noise characteristics; Circuit noise; Computational Intelligence Society; Dielectric substrates; Inductors; Integrated circuit interconnections; Noise figure; Parasitic capacitance; Polyimides; Silicon; Thermal resistance;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824285
