Parallel test method for NoC-based SoCs

Author

Ansari, M.A. ; Jeahoon Song ; Minchul Kim ; Sungju Park

Author_Institution

Dept. of Comput. Sci. & Eng., Hanyang Univ., Ansan, South Korea

fYear

2009

Firstpage

116

Lastpage

119

Abstract

Reusing on-chip functional interconnects as test access mechanism (TAM) appeared usual these days. One of the most important functional interconnects for highly crowded future system-on-chips (SoCs) is network-on-chip (NoC). Several NoC architectures including router and network interface (NI) have been proposed. They allow narrowcast and multicast of packets, in-order packet delivery, guaranteed throughput and best-effort services. Exploiting the preceding research, we present here a parallel test method and a manipulated scheduling method for NoC-based SoCs, while reusing NoC as TAM, with the goal of reducing overall test time. The proposed test method is compared with previous works using some of ITC´02 benchmark circuits which showed significant test time reduction.

Keywords

integrated circuit interconnections; logic testing; network-on-chip; ITC´02 benchmark circuits; NoC architectures; NoC-based SoC; best-effort services; guaranteed throughput; highly crowded future system-on-chips; in-order packet delivery; network interface; network-on-chip; on-chip functional interconnects; parallel test method; router; scheduling method; test access mechanism; test time reduction; Circuit testing; Clocks; Integrated circuit interconnections; Network interfaces; Network-on-a-chip; Power system interconnection; Protocols; Scheduling algorithm; System-on-a-chip; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2009 International

Conference_Location

Busan

Print_ISBN

978-1-4244-5034-3

Electronic_ISBN

978-1-4244-5035-0

Type

conf

DOI

10.1109/SOCDC.2009.5423885

Filename

5423885