InP DHBT IC Technology with Implanted Collector Pedestal and Electroplated Device Contacts

Author

Urteaga, M. ; Shinohara, K. ; Pierson, R. ; Rowell, P. ; Brar, B. ; Griffith, Z. ; Parthasarathy, N. ; Rodwell, M.

Author_Institution

Rockwell Sci. Co., Thousand Oaks, CA

fYear

2006

Firstpage

187

Lastpage

190

Abstract

The authors report an InP DHBT IC technology that incorporates an ion implanted N+ collector-pedestal for collector-base capacitance (C _cb) reduction. The technology utilizes electroplating processes and sidewall spacers to form a high yield self-aligned base-emitter junction. Devices with 0.4 mum emitter junction widths demonstrate peak f_t and f_max values of over 370 GHz. The devices demonstrate a ~35% reduction in C_cb versus HBTs with the same device footprint fabricated without a collector pedestal. A current mode logic (CML) divide-by-two circuit demonstrated a maximum operating frequency of 128 GHz, a -20% improvement versus the same design realized in a non-collector-pedestal process

Keywords

III-V semiconductors; bipolar logic circuits; electroplating; emitter-coupled logic; heterojunction bipolar transistors; indium compounds; ion implantation; DHBT integrated circuit; InP; base-emitter junction; collector-base capacitance; current mode logic; electroplated device contacts; electroplating process; implanted collector pedestal; ion implantation; self-aligned junction; sidewall spacers; Bipolar integrated circuits; Capacitance; DH-HEMTs; Frequency conversion; Heterojunction bipolar transistors; Indium phosphide; Ion implantation; Logic circuits; Ohmic contacts; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium, 2006. CSIC 2006. IEEE

Conference_Location

San Antonio, TX

Print_ISBN

1-4244-0126-7

Electronic_ISBN

1-4244-0127-5

Type

conf

DOI

10.1109/CSICS.2006.319893

Filename

4110015