Title :
Line inductance extraction and modeling in a real chip with power grid
Author :
Kleveland, B. ; Xiaoning Qi ; Madden, L. ; Dutton, R.W. ; Wong, S.S.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
A realistic power grid and pseudo-random signal lines connected to on-chip drivers are included for accurate extraction of the parasitic inductance in a 5-metal layer 0.25-/spl mu/m CMOS technology. A new ring oscillator for the extraction of signal delay and characteristic impedance is demonstrated. The increase of signal delay due to mutual inductance of clock lines is measured directly with S-parameter characterization techniques.
Keywords :
CMOS digital integrated circuits; S-parameters; driver circuits; inductance; integrated circuit modelling; 0.25 micron; CMOS chip; S-parameter; characteristic impedance; clock line; mutual inductance; on-chip driver; parameter extraction; parasitic inductance; power grid; pseudo-random signal line; ring oscillator; signal delay; Circuit simulation; Circuit testing; Flowcharts; Frequency; Inductance; Power grids; Ring oscillators; SPICE; Switches; Wires;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824294
