Title :
0.1-/spl mu/m CMOS technology for high-speed logic and system LSIs with SiO/SiN/poly-Si/W gate-system
Author :
Onai, T. ; Tsujikawa, S. ; Uchino, T. ; Tsuchiya, R. ; Ohnishi, K. ; Fukuda, H. ; Hisamoto, D. ; Yamamoto, N. ; Yugami, J. ; Ichinose, K. ; Ootsuka, F.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
0.1-/spl mu/m CMOS devices for high speed logic and system LSIs have been successfully achieved. The device has an SiO/SiN stacked gate dielectric with T/sub oxinv/=2.8 nm to avoid gate direct tunneling leakage and boron penetration. It also utilizes a poly/metal stacked gate electrode to reduce gate resistance. Carefully optimized source/drain extensions and punch-through stoppers offer good short channel operation below 0.1-/spl mu/m gate length and high-drive currents of 1000 /spl mu/A//spl mu/m for NMOSs and 410 /spl mu/A//spl mu/m for PMOSs at 1.5 V voltage supply.
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; high-speed integrated circuits; integrated circuit technology; large scale integration; 0.1 micron; 1.5 V; 2.8 nm; CMOS technology; NMOSFETs; PMOSFETs; SiO-SiN-Si-W; SiO/SiN stacked gate dielectric; SiO/SiN/poly-Si/W gate-system; gate resistance reduction; high-drive currents; high-speed logic LSIs; high-speed system LSIs; optimized source/drain extensions; polysilicon/metal stacked gate electrode; punch-through stoppers; short channel operation; Boron; CMOS logic circuits; CMOS technology; Contact resistance; Dielectrics; Electrodes; Large scale integration; MOS devices; Silicon compounds; Tunneling;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824304
