Title :
A 6.25Gb/s Decision Feedback Equalizer in 0.18??im CMOS Technology for High-Speed SerDes
Author :
Feng, Zhuangjing ; Hu, Qingsheng
Author_Institution :
Inst. of RF& OE-ICs, Southeast Univ., Nanjing, China
Abstract :
In this paper a 6.25Gb/s two-tap half-rate decision feedback equalizer (DFE) is designed and implemented in TSMC 0.18μm CMOS technology. After system-level simulation based on Simulink and pre-simulation, the DFE architecture is designed and corresponding parameters are determined. To achieve high data rate, CML DFFs, summers and multiplex are all designed elaborately. The total area including I/O pads is 0.3×0.5μm2. Post simulation results show that the horizontal eye opening of recovered data is 0.7 UI at 6.25Gb/s.
Keywords :
CMOS integrated circuits; decision feedback equalisers; multiplexing equipment; DFE architecture; Simulink; TSMC CMOS technology; bit rate 6.25 Gbit/s; high-speed SerDes; multiplexer; size 0.18 mum; system-level simulation; two-tap half-rate decision feedback equalizer; CMOS integrated circuits; CMOS technology; Clocks; Decision feedback equalizers; Delay; Simulation;
Conference_Titel :
Wireless Communications, Networking and Mobile Computing (WiCOM), 2011 7th International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-6250-6
DOI :
10.1109/wicom.2011.6040223
