Cascaded Time Difference Amplifier using Differential Logic Delay Cell

We introduce a 4²Ã— cascaded time difference amplifier (TDA) using differential logic delay cells with 0.18 ¿m CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ± 250 ps input range. Also the charge pump current of PMOS and NMOS unbalance can adjust the TD gain.