• DocumentCode
    1647372
  • Title

    DVGen: Increasing Coverage by Automatically Combining Test Specifications

  • Author

    Rich, Kevin D. ; Shaw, Robert ; Govindaraju, Shankar G. ; Dobrikin, David

  • Author_Institution
    Transmeta Corp., Santa Clara, CA
  • fYear
    2006
  • Firstpage
    3
  • Lastpage
    10
  • Abstract
    DVGen is a novel microprocessor test generator that allows the verification engineer to focus only on capturing test intent via minimally constrained test specifications. DVGen combines test specifications to generate tests that preserve the intent of each specification while causing the concurrent occurrence of interesting events from each specification. DVGen is very effective at uncovering multi-dimensional corner case bugs, which have historically been the bane of complex designs
  • Keywords
    computer debugging; formal specification; formal verification; logic testing; microprocessor chips; DVGen; microprocessor test generator; multidimensional corner case bugs; test specification; Automatic testing; Computer bugs; Conferences; Design engineering; Engines; Instruction sets; Microprocessors; Scheduling; Silicon; VLIW;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
  • Conference_Location
    Monterey, CA
  • ISSN
    1552-6674
  • Print_ISBN
    1-4244-0679-X
  • Electronic_ISBN
    1552-6674
  • Type

    conf

  • DOI
    10.1109/HLDVT.2006.320011
  • Filename
    4110052
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1647372