Title :
Trends in Test: Challenges and Techniques
Author_Institution :
Synopsys, Inc, Mountain View, CA
Abstract :
Summary form only given. Ever increasing design sizes and the need for more sophisticated fault models at smaller process geometries require the use of compression technology to reduce the size of the ATPG pattern set. Otherwise those don´t fit on the automated test equipment. Compression is becoming the norm on the most advanced chips and is the enabling technology for true at speed testing of very large deep submicron designs. In this talk, the author reviews challenges and techniques for high quality at speed test at 90nm and below
Keywords :
automatic test pattern generation; fault diagnosis; logic design; logic testing; ATPG pattern set; automated test equipment; compression technology; fault model; Automatic test pattern generation; Conferences; Geometry; Solid modeling; Test equipment; Testing;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0680-3
Electronic_ISBN :
1552-6674
DOI :
10.1109/HLDVT.2006.319998
