DocumentCode
1647541
Title
Formal Verifications in Modern Chip Designs
Author
Khoo, Kei-Yong
Author_Institution
Cadence Design Syst., Inc., San Jose, CA
fYear
2006
Firstpage
38
Lastpage
38
Abstract
Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, design-constraint management, and low-power design verifications. In addition, we examine modern and emerging design styles and techniques, and requirements on formal technologies to meet the new verification challenges
Keywords
formal verification; logic design; logic testing; low-power electronics; design-constraint management; formal verification; logic equivalence checking; low-power design verification; modern chip design; Chip scale packaging; Conferences; Formal verification; Logic design; Power system management; System testing; Technology management;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
Conference_Location
Monterey, CA
ISSN
1552-6674
Print_ISBN
1-4244-0679-X
Electronic_ISBN
1552-6674
Type
conf
DOI
10.1109/HLDVT.2006.320001
Filename
4110059
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