Title :
Layout-level techniques for testability improvement of MOS physical designs
Author :
Santos, M.B. ; Concalves, F.M. ; Sousa, J.J.T. ; Teixeira, J.P.
Author_Institution :
INESC, IST, CEAUTL, Lisbon, Portugal
Abstract :
A methodology for physical testability assessment is reviewed, and a technique to enhance the physical testability of ICs with BIST (built-in self test) is presented. It is shown that an appropriate choice of a primitive polynomial can improve the realistic fault coverage, obtained with pseudorandom test patterns or, conversely, can lead to reduced test lengths, for the same fault coverage. The results are ascertained by the physical design and linear feedback shift register specification of a self-test ALU (arithmetic logic unit)
Keywords :
MOS integrated circuits; built-in self test; circuit layout; digital integrated circuits; integrated circuit testing; BIST; ICs; MOS physical designs; arithmetic logic unit; built-in self test; digital IC; fault coverage; linear feedback shift register specification; physical testability assessment; primitive polynomial; pseudorandom test patterns; self-test ALU; testability improvement; Analytical models; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Fault detection; Fault diagnosis; Integrated circuit testing; Semiconductor device modeling;
Conference_Titel :
Electrotechnical Conference, 1991. Proceedings., 6th Mediterranean
Conference_Location :
LJubljana
Print_ISBN :
0-87942-655-1
DOI :
10.1109/MELCON.1991.161823
