On the Automatic Transactor Generation for TLM-based Design Flows

Transaction level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems design and verification. It allows designers to focus on the functionalities of the design, while abstracting away implementation details that are added at lower abstraction levels. A TLM-based design flow can afford several advantages, such as, TLM-RTL mixed simulation, testbench and assertion reuse by exploiting the transactor concept. Nevertheless, transactors implementation and verification are duty of designers so far and their generation effort often overcomes the benefits of the TLM-based design adoption. In this paper a methodology is proposed to automate some parts of the transactor generation aiming at reaching their correct-by-construction implementation. The methodology relies on (i) the adoption of a TLM API standard to ensure a correct refinement degree of transactors and (ii) the extended finite state machine (EFSM) model to formally represent the communication environment through the generation process