DocumentCode :
1647801
Title :
Addressing Test Generation Challenges for Configurable Processor Verification
Author :
Rimon, M. ; Lichtenstein, Y. ; Adir, A. ; Jaeger, I. ; Vinov, M. ; Johnson, S. ; Jani, D.
Author_Institution :
IBM Res. Lab. in Haifa
fYear :
2006
Firstpage :
95
Lastpage :
101
Abstract :
Having only recently entered the mainstream, configurable processor technology already provides practical automated hardware design. In this paper, we address the challenges of verifying these software-constructed hardware artifacts and show that sophisticated automation is mandatory. We describe how a model-based test generation technology was integrated into the verification flow of a configurable processor design. We report on experiments with two complex verification tasks. In both experiments, the model-based technology has achieved much higher coverage than standard verification tools and required considerably fewer engineering resources. We conclude that processor-oriented test generation technology addresses well the challenges of verifying automated hardware design
Keywords :
automatic test pattern generation; circuit CAD; formal verification; reconfigurable architectures; automated hardware design verification; configurable processor design verification flow; model-based test generation; processor-oriented test generation; software-constructed hardware artifact verification; sophisticated automation; Application software; Application specific processors; Automation; Conferences; Electronic mail; Hardware; Laboratories; Reduced instruction set computing; Silicon; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
Conference_Location :
Monterey, CA
ISSN :
1552-6674
Print_ISBN :
1-4244-0680-3
Electronic_ISBN :
1552-6674
Type :
conf
DOI :
10.1109/HLDVT.2006.319970
Filename :
4110069
Link To Document :
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