A 100-Gbit/s 2:1 multiplexer in InP HEMT technology

Author

Suzuki, T. ; Nakasha, Y. ; Sakoda, T. ; Sawada, K. ; Takahashi, T. ; Makiyama, K. ; Hirose, T. ; Takigawa, M.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

Volume

2

fYear

2003

Firstpage

1173

Abstract

In this paper, we describe a 100-Gbit/s 2:1 multiplexer (MUX). In order to suppress the degradation of signals and to increase the operation speed, we designed interconnections for the circuit using impedance matching techniques. We fabricated the MUX with 0.13-/spl mu/m InP HEMT technology, which has a cutoff frequency of 175 GHz. By using this design, we succeeded in 100-Gbit/s operation of the MUX and obtained clear eye waveforms. We also developed a V-connector module for the circuit, and achieved 80-Gbit/s operation.

Keywords

HEMT integrated circuits; III-V semiconductors; field effect digital integrated circuits; high-speed integrated circuits; impedance matching; indium compounds; integrated circuit design; integrated circuit interconnections; multiplexing equipment; 0.13 micron; 100 Gbit/s; 100-Gbit/s 2:1 multiplexer; 175 GHz; 80 Gbit/s; InAlAs-InGaAs-InP; InP; InP HEMT technology; V-connector module; circuit interconnections; clear eye waveforms; cutoff frequency; high-speed digital circuits; impedance matching techniques; operation speed; signal degradation suppression; Capacitance; Capacitors; Clocks; Cutoff frequency; HEMTs; Heterojunction bipolar transistors; Indium phosphide; Integrated circuit interconnections; Multiplexing; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2003 IEEE MTT-S International

Conference_Location

Philadelphia, PA, USA

ISSN

0149-645X

Print_ISBN

0-7803-7695-1

Type

conf

DOI

10.1109/MWSYM.2003.1212577

Filename

1212577