DocumentCode
1647938
Title
Comparative analysis of adiabatic logic styles
Author
Arsalan, Muhammad ; Shams, Maitham
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fYear
2004
Firstpage
663
Lastpage
668
Abstract
Over the past decade, different adiabatic logic styles for low-power applications have been published. This paper compares and analyzes the performance and energy dissipation of various adiabatic logic styles in a uniform test environment. The test benches are laid out and a test chip has been fabricated in a standard 0.18 μm CMOS technology. The results are mainly based on test chip measurements and post layout simulations.
Keywords
CMOS logic circuits; benchmark testing; integrated circuit testing; low-power electronics; network analysis; 0.18 mum; CMOS technology; adiabatic logic styles; comparative analysis; low-power applications; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Clocks; Diodes; Energy dissipation; Logic circuits; Logic testing; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Multitopic Conference, 2004. Proceedings of INMIC 2004. 8th International
Print_ISBN
0-7803-8680-9
Type
conf
DOI
10.1109/INMIC.2004.1492971
Filename
1492971
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