MMV: Metamodeling Based Microprocessor Valiation Environment

With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges. The systematic validation approach starts with defining the correct behaviors of the hardware and software components and their interactions. This requires a new modeling paradigm that supports multiple levels of abstraction. Mutual consistency of models at adjacent levels is crucial for manual refinement of models from the full chip level to production RTL, which is likely to remain the dominant design methodology of complex microprocessors in the near future. In this work, we present MMV, a validation environment based on metamodeling, that can be used to create models at various, abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage and test generation tools. We illustrate the functionalities in MMV by modeling a 32 bit RISC processor at the system, instruction set architecture and microarchitecture levels. We show by examples how consistency across levels is enforced during modeling and also how to generate constraints for automatic test generation