1.4-W 50-Gbit/s InP HEMT 1:4 demultiplexer IC with a multi-phase clock architecture

Author

Sano, K. ; Murata, K. ; Kitabayashi, H. ; Sugitani, S. ; Sugahara, H. ; Enoki, T.

Author_Institution

NTT Photonics Labs., NTT Corp., Kanagawa, Japan

Volume

2

fYear

2003

Firstpage

1181

Abstract

High-speed and low-power operation of a 1:4 demultiplexer IC with a multi-phase clock (MPC) architecture is reported. The architecture features four parallel latch lines and a toggle flip-flop (TFF) that generates a four-phase clock. The IC, which was fabricated using InP HEMTs, exhibited 50-Gbit/s error-free operation with a power consumption of 1.42 W. Compared to a conventional tree-type InP HEMT 1:4 demultiplexer IC, the IC with the MPC architecture operates at the same operating speed with only one-quarter the power consumption.

Keywords

HEMT integrated circuits; III-V semiconductors; clocks; demultiplexing equipment; field effect digital integrated circuits; flip-flops; high-speed integrated circuits; indium compounds; low-power electronics; time division multiplexing; 1.42 W; 50 Gbit/s; InP; InP HEMT 1:4 demultiplexer IC; electrical-time-division multiplexing; error-free operation; four-phase clock; high-speed low-power operation; multi-phase clock architecture; operating speed; optical communication systems; parallel latch lines; power consumption; toggle flip-flop; Clocks; Electronic mail; Energy consumption; Flip-flops; HEMTs; High speed integrated circuits; Indium phosphide; Laboratories; Latches; Photonic integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2003 IEEE MTT-S International

Conference_Location

Philadelphia, PA, USA

ISSN

0149-645X

Print_ISBN

0-7803-7695-1

Type

conf

DOI

10.1109/MWSYM.2003.1212579

Filename

1212579