Title :
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler
Author :
Gyeonghoon Kim ; Seongwook Park ; Kyuho Lee ; Youchang Kim ; Injoon Hong ; Kyeongryeol Bong ; Dongjoo Shin ; Sungpill Choi ; Junyoung Park ; Hoi-Jun Yoo
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Abstract :
A 36 Heterogeneous multicore processor is proposed to accelerate recognition-based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task-level pipeline. As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state-of-the-art augmented reality processor, for 30fps 720p test input video.
Keywords :
augmented reality; energy conservation; image processing; low-power electronics; multiprocessing systems; network-on-chip; object recognition; 2D-mesh network-on-chip; DLP; SIMD processing elements; TLP; congestion-aware network-on-chip scheduler; data level parallelism; energy efficiency; heterogeneous multicore processor; internal data transaction; recognition-based markerless augmented reality; single instruction multiple data processing elements; task level parallelism; task-level pipelined many-SIMD augmented reality processor; task-level pipelined multicore architecture; test input video; Acceleration; Augmented reality; Multicore processing; Network-on-chip; Real-time systems; Throughput; 2D-mesh NoC; augmented reality; dynamic resource management; heterogeneous multicore; network-on-chip scheduler; object recognition;
Conference_Titel :
COOL Chips XVII, 2014 IEEE
Conference_Location :
Yokohama
DOI :
10.1109/CoolChips.2014.6842959
