DocumentCode
164801
Title
A low power NoC router using the marching memory through type
Author
Yasudo, Ryota ; Kagami, Takahiro ; Amano, Hideharu ; Nakase, Yasunobu ; Watanebe, Masashi ; Oishi, Tsukasa ; Shimizu, Tsuyoshi ; Nakamura, T.
Author_Institution
Keio Univ., Yokohama, Japan
fYear
2014
fDate
14-16 April 2014
Firstpage
1
Lastpage
3
Abstract
We have concluded that with a router using MMTH the power consumption is associated with the bit change rate of the data, and when NAS parallel benchmarks work on NoC, it is reduced by 42.4% on average at 2GHz compared with a traditional FIFO implementation. The performance degradation caused by the delay of the reading time can be mostly saved by the look-ahead technique in the router.
Keywords
low-power electronics; network routing; network-on-chip; semiconductor storage; look ahead technique; low power NoC router; marching memory through type; performance degradation; power consumption; reading time delay; Benchmark testing;
fLanguage
English
Publisher
ieee
Conference_Titel
COOL Chips XVII, 2014 IEEE
Conference_Location
Yokohama
Type
conf
DOI
10.1109/CoolChips.2014.6842960
Filename
6842960
Link To Document