An accurate simulation technique for short-circuit power dissipation based on current component isolation

A circuit simulation technique is presented which permits the measurement of the average short-circuit power dissipation component in integrated circuits. This technique is most appropriate for low-power circuit design and can be applied effectively to any complementary circuit structure, such as CMOS, that does not permit current flow (other than leakage current) during steady-state operation. Short-circuit power dissipation expressions are derived, and SPICE simulation results for a differently ratioed W_p/W_n circuit are shown