Panel: Assertion-Based Verification -What´s the Big Deal?

Summary form only given. Assertion based validation of hardware and software systems has been in use in the industry for a long time. In the software languages such as C++ or Java, there are special assert constructs that are used to specify a Boolean condition. These conditions express what the programmers think ought to hold, at specific points in their programs. Violations of such assertions provide clues about the program state at those points during execution and hence indicate the existence of bugs. In hardware design especially at the RTL and higher abstraction levels, similar assertions have been used originally in proprietary languages, and more recently with PSL (Property Specification Language). PSL was standardized initially by Accellera, and later by IEEE. PSL and similar assertion languages allow not only Boolean expressions, but more complex constructs involving temporal behaviors. Therefore, these languages can be used for checking assertions at certain points of the model execution, as well as for formal property verification. Standardization of PSL gave rise to a lot of interest in the hardware design industry, and various formal and simulation based techniques have been integrated into the validation tools from the various EDA companies. The question in front of the panel is if the assertion based verification a panacea for the validation gap problem in the design industry, and if not, where the short comings are. Industry experts from Synopsys, Cadence, Mentor Graphics, Real Intent, and from Academia debated these questions at this panel