• DocumentCode
    1648397
  • Title

    Interconnection delays in hierarchical timing simulation

  • Author

    Caisso, J.-P. ; Cerny, E. ; Rumin, N.C.

  • Author_Institution
    Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
  • fYear
    1989
  • Firstpage
    1162
  • Abstract
    A simple and efficient method has been developed for computing interconnection delays in an event-driven hierarchical simulator, when multiple driving sources are present. The theory is based on T.M. Lin and C.A. Mead´s algorithm (see IEEE Trans. Comput.-Aided Design, vol. CAD-5, p.188-197, 1986) for computing delays in general RC networks by converting them to trees using node splitting. However, their algorithm requires iteration to solve the resulting linear system of equations. The present technique requires no iteration and yet gives the same results. The accuracy improves as technology is scaled down and when interconnection delays dominate
  • Keywords
    circuit CAD; delays; digital simulation; network topology; trees (mathematics); event-driven hierarchical simulator; hierarchical timing simulation; interconnection delays; linear system; multiple driving sources; node splitting; trees; Capacitance; Computer networks; Delay; Equations; Integrated circuit interconnections; Inverters; Iterative methods; Laboratories; Linear systems; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1989., IEEE International Symposium on
  • Conference_Location
    Portland, OR
  • Type

    conf

  • DOI
    10.1109/ISCAS.1989.100559
  • Filename
    100559