Title :
A parallel implementation of large-scale circuit simulation
Author :
Yoshida, Hisato ; Kumagai, Sadatoshi ; Shirakawa, Lsao ; Kodama, Shinzo
Author_Institution :
Dept. of Electron. Eng., Osaka Univ., Japan
Abstract :
An efficient hierarchical parallel implementation of LSI circuit simulation is presented. The block Gauss-Seidel waveform relaxation algorithm is adopted as the first-level parallel computation and is combined with the second-level pipelining and parallel schemes in the various phases of a direct analysis of each subcircuit. Experimental results demonstrating the effective parallelism and the time cost reduction by the proposed methods are presented.<>
Keywords :
digital simulation; large scale integration; parallel processing; LSI; block Gauss-Seidel waveform relaxation algorithm; direct analysis; first-level parallel computation; large-scale circuit simulation; parallel implementation; second-level pipelining; time cost reduction; Algorithm design and analysis; Circuit simulation; Computational modeling; Concurrent computing; Costs; Gaussian processes; Large-scale systems; Parallel processing; Pipeline processing; Processor scheduling;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.14930
