Title :
Reduction of random telegraph noise in High-к / metal-gate stacks for 22 nm generation FETs
Author :
Tega, N. ; Miki, H. ; Ren, Z. ; Emic, C. P D ; Zhu, Y. ; Frank, D.J. ; Cai, J. ; Guillorn, M.A. ; Park, D.-G. ; Haensch, W. ; Torii, K.
Author_Institution :
Semicond. Innovation Res. Project, Hitachi America Ltd., Yorktown Heights, NY, USA
Abstract :
This work demonstrates, for the first time, the reduction of random telegraph noise (RTN) in high-κ/metal gate (HK/MG) stacks incorporated in 22 nm generation FETs. Many thousands of such FETs have been fabricated, measured, and analyzed using a statistical technique to separate RTN as a major noise component from 1/f noise as a minor component. Based on a statistical comparison of these FETs, we find that high temperature forming gas annealing can suppress RTN threshold voltage variation (ΔVth). In addition, properly annealed HK FETs have smaller RTN ΔVth than SiON FETs, due mostly to fewer traps and partly to thinner inversion thickness in HK/MG. Based on these results, we project that random dopant fluctuations will have a greater impact on SRAM yield than RTN until at least the 15 nm generation, for doped channel FETs.
Keywords :
1/f noise; SRAM chips; annealing; doping; field effect transistors; high-k dielectric thin films; silicon compounds; statistical analysis; 1/f noise; HK/MG stacks; RTN threshold voltage variation; SRAM yield; SiON FET; doped channel FET; high temperature forming gas annealing; high-κ/metal-gate stacks; high-spl kappa//metal gate stacks; noise component; random dopant fluctuations; random telegraph noise reduction; size 22 nm; statistical technique; Annealing; FETs; Fluctuations; Noise generators; Noise measurement; Noise reduction; Random access memory; Telegraphy; Temperature distribution; Threshold voltage;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424225