Reliability of barrier engineered charge trapping devices for sub-30nm NAND flash

Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can improve the erase characteristics, but the high electric field for electron de-trapping degrades reliability. Barrier engineering improves reliability by allowing hole erasing instead of high-field detrapping. In extreme scaling to < 20nm nodes, few-electron statistical fluctuation issues and random telegraph noise (RTN) are concerns but CT devices are still quite robust. TFT CT devices are also well suited for 3D scaling.