DocumentCode
1649663
Title
Electrically modifiable nonvolatile synapses for neural networks
Author
White, Marvin H. ; Chen, Chun-Yu
Author_Institution
Lehigh Univ., Bethlehem, PA, USA
fYear
1989
Firstpage
1213
Abstract
The realization of an electronic element to simulate the synaptic interconnect in an electronic neural system is addressed. The basic interconnect or weight is an electrically reprogrammable, nonvolatile, analog conductance for the adaptive (modifiable) synapse. This weight is formed with a multidielectric, SONOS memory transistor which may be programmed at 5-V levels compatible with CMOS VLSI technology. The attractive features of this synaptic weight are its low power dissipation, small size, low voltage programmability, wide dynamic range, and ability to mimic biological synapses with respect to memory retention. Also addressed is the incorporation of the basic electronic synapse into a Widrow-Hoff delta-rule algorithm to study the electrical characteristics of this synthetic element in a single-level adaptive linear neuron. The combination of synaptic weights and a control algorithm provides a means to examine a basic functional neural building block for neural networks
Keywords
CMOS integrated circuits; VLSI; adaptive systems; memory architecture; neural nets; CMOS VLSI technology; SONOS memory transistor; Widrow-Hoff delta-rule algorithm; analog conductance; electrically reprogrammable; electronic neural system; functional neural building block; neural networks; power dissipation; single-level adaptive linear neuron; synaptic interconnect; voltage programmability; CMOS technology; Dynamic range; Electric variables; Low voltage; Neural networks; Nonvolatile memory; Power dissipation; Power system interconnection; SONOS devices; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location
Portland, OR
Type
conf
DOI
10.1109/ISCAS.1989.100572
Filename
100572
Link To Document