• DocumentCode
    1650154
  • Title

    Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts

  • Author

    Lu, Shun-Yen ; Hsieh, Pei-Ying ; Liou, Jing-Jia

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
  • fYear
    2006
  • Firstpage
    100
  • Lastpage
    106
  • Abstract
    It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target path can then be validated through simple calculation. Yet, no decomposition process is available to find paths that satisfy the above property. In this paper, given a set of target critical paths, we propose a two-stage method to find a set of robust-testable paths (with smaller number than the original set). The first stage constructs a necessary subset for critical robust paths, and the second stage identifies remaining functional sensitizable segments and their corresponding composing robust paths. The experiments show that a large percentage (several benchmarks close to 100%, 75% on average) of critical paths can be covered for most circuits. All paths and coverage are verified to match the best possible results. The data also indicate that the remaining hard-to-test (functional sensitizable) paths actually result from only a few tens of segments in the circuit (except for one circuit, s35932). DfT technique can then be applied to these uncovered segments for full testability with small overheads
  • Keywords
    circuit testing; delay circuits; design for testability; fault diagnosis; critical path delay fault; critical robust path; design for testability; hard-to-test path; robust-testable path; sensitizable segment; Automatic test pattern generation; Circuit faults; Circuit optimization; Circuit testing; Delay; Robustness; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    1-59593-389-1
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2006.320072
  • Filename
    4110160