Title :
Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
Author :
Ragnarsson, L. Å ; Li, Z. ; Tseng, J. ; Schram, T. ; Rohr, E. ; Cho, M.J. ; Kauerauf, T. ; Conard, T. ; Okuno, Y. ; Parvais, B. ; Absil, P. ; Biesemans, S. ; Hoffmann, T.Y.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS VT of 0.3/-0.4V, good VT-uniformity, and VT-matching and very high cutoff frequencies at ˜290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.
Keywords :
CMOS integrated circuits; circuit optimisation; circuit reliability; hafnium compounds; silicon compounds; CMOS; HfO2; SiGe; TDDB lifetimes; cutoff frequency; drive currents; gate first integration approach; gate-electrode optimization; nMOS devices; pMOS devices; reliability challenges; replacement poly gate process; size 38 nm; ultra low-EOT; zero interface layer; Capacitance; Capacitance-voltage characteristics; Cutoff frequency; Electrodes; Germanium silicon alloys; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOS devices; Silicon germanium;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424254
