Title :
Future directions of non-volatile memory in compute applications
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
NAND´s new position in the compute memory hierarchy imposes new considerations for scaling to smaller lithography nodes and tightly links NAND with the external controller. Likewise, widespread acceptance of future NVM in the compute memory hierarchy will be determined by ability to meet both cost and performance criteria.
Keywords :
random-access storage; compute memory hierarchy; nonvolatile memory; smaller lithography nodes; Application software; Computer applications; Costs; Delay; Educational institutions; Hard disks; Lithography; Nonvolatile memory; Random access memory; Writing;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424257
