Title :
Challenges in verifying an integrated 3D design
Author :
Yip, Tsunwai Gary ; Hung, Chuan Yung ; Iyengar, Venu
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
The integrated 3D configuration considered in this study includes a silicon die on one side of an organic interposer and a different die on the other side. The three parts are from three different design environments, each has its own database and description language not compatible with the other two. The incompatibility triggered a search for a new methodology for the physical verification of the 3D configuration. Application scripts were developed and successfully used to verify the physical connections within the complex design of the interposer, which accommodates 1600 signals and 12,000 traces for connecting the signals between the two chips. The layout of 56,000 vias for power and signal was also verified to meet the requirements for the manufacturing of the organic interposer.
Keywords :
integrated circuit design; silicon; three-dimensional integrated circuits; description language; design environments; integrated 3D configuration; integrated 3D design; organic interposer; physical connections; physical verification; silicon die; Design automation; Integrated circuit interconnections; Silicon; Substrates; System analysis and design; System-on-a-chip; Three dimensional displays; 3D design; integration; system design; verification;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Conference_Location :
Dresden
Print_ISBN :
978-1-4577-2145-8
DOI :
10.1109/DATE.2012.6176454
